Within the field of electronic integrated circuitry, there exists a need for accurate positioning and bonding of circuit components to ensure circuit integrity and proper operation. One example of this accuracy requirement involves integrated circuit chips which must be accurately located within and bonded to ceramic chip carriers. The ceramic chip carriers typically must then be accurately located within and bonded to next-level-of-packaging components, such as printed circuit boards.
Typical electronic chips and chip carriers may include hundreds of bonding points which require considerable alignment accuracy to be functional. In many cases, the positioning and bonding of these chips and chip carriers is hampered by next-level-of-packaging components which have misaligned bonding pads or leads. Frequently such misalignment is caused by the shrinkage of ceramic carriers during manufacture. Indeed, each ceramic chip carrier may shrink on the average of 15% of total size during the firing portion of manufacture. Such shrinkage is well known in the field of chip carrier production, and shrinkage tolerance specifications are generally specified. Nevertheless, a sizable number of ceramic chip carriers experience unacceptably large shrinkage distortions and must be rejected. These rejections result in substantial inefficiencies and expense due to product loss and wasted production time. Moreover, with the development of higher density and finer pitch lead environments in electronic circuitry, there is an enhanced need for a solution to this packaging problem.
What has been needed, therefore, is a system for arranging bonding points between integrated circuit components for functional use independent of carrier shrinkage tolerances. What has been further needed is a system for arranging bonding points on an integrated circuit board footprint for functional receipt and bonding of electronic components independent of component or circuit board shrinkage tolerances.
What has been further needed is a method to very precisely position and bond integrated circuit components with next-level-of-packaging independent of component or package shrinkage tolerances.